The move from 224G to 448G sounds routine: one more doubling of lane rate. The OIF's CEI-448G framework does not read that way. Its opening page says "a consensus has been reached that new specifications and technologies will be necessary" [1]. That is a loaded sentence from a standards body. The reason is AI. 448G is not simply 224G running faster: the signalling format, the error code, the channel budget and what "copper" even means all change at once, each trading against power.
Why AI is forcing the lane rate higher
Frontier models no longer fit on one accelerator, so they are split across many. The network joining them carries most of a cluster's interconnect bandwidth and must stay lossless. Today that network spans about 100 accelerators in a rack; the next generation is aiming at roughly 1,000, spread across a row [1]. NVIDIA's NVL72 already puts 72 GPUs and 130 TB/s of NVLink into one rack [2], and UALink 200G 1.0 spans up to 1,024 accelerators [3]. Each step multiplies the bandwidth that network has to carry. The space for it does not grow: every accelerator still connects through the same connectors, cables and board area.
Why not just add more lanes? Because each lane needs its own share of that space, and spending it gets you fewer accelerators per rack [1]. If the rack must hold more, the bandwidth must come from lane rate. That is what preserves density as the AI fabric grows.
That increase in lane rate brings five changes into focus: signalling, error correction, channel loss, the physical copper path, and the power trade-offs between copper implementations.
1. The signalling format may change
At 448G, PAM4 stops being the automatic choice. A PAM4 lane at 448G runs at 224 GBd, which puts its Nyquist frequency at 112 GHz [1], and the channel has to carry useful signal up to roughly that point. The best channels OIF members could show rolled off at 75 to 80 GHz in October 2024, and reached about 100 GHz a year later [4]. That gap is the problem.
Higher-order formats such as PAM6 and PAM8 close the gap by packing more bits into each symbol. Fewer symbols per second means a lower Nyquist frequency, about 87 GHz for PAM6 and 75 GHz for PAM8 (Figure 1), which brings the signal back inside what today's channels can carry. The cost is signal-to-noise: more levels in the same voltage swing leave less margin between them, roughly 4.4 dB less for PAM6 and 7.4 dB less for PAM8 than for PAM4 [13]. Nobody has picked a format yet. The choice was still open in mid-2026, and it may split by reach rather than resolve, with one format for short links and another for long [14].
2. Error correction gets stronger, and it is not free
Whichever format wins, the receiver will see more raw bit errors than at 224G. The usual answer is stronger forward error correction (FEC): extra bits sent with the data let the receiver find and fix errors, at a cost in latency and power.
That trade is already visible in 802.3dj, the IEEE amendment that defines 200G-per-lane Ethernet. Its outer code is the familiar RS (544,514), known as KP4. For 200G optical links, 802.3dj adds a second, lighter code between it and the channel: a Hamming (128,120) inner code that runs inside the module's DSP. The inner code cleans up most errors first, and KP4 handles what is left. Together, they let the link tolerate roughly twenty times as many raw errors as KP4 alone, in the cases studied in [5].
The price is latency. The inner code adds roughly 10 ns. Errors at these speeds tend to arrive in bursts, so the code also needs an interleaver, which spreads each burst across many codewords so that no single one is overwhelmed. With the interleaver, the added latency is about 56 ns [5]. That matters in AI training, where collective operations such as all-reduce cannot finish until the slowest transfer does.
The same pressure is now reaching electrical links. At 448G, the OIF expects that KP4 alone will no longer be enough [1]. The open question is how much stronger the code should be, and here power sets the limit. As Cathy Liu, OIF's vice president, puts it: "The key is not to overdo it, as the price is greater power consumption" [4].
3. The channel budget gets much harder
Every link has a loss budget: how much signal the channel (traces, connectors and cable) can absorb before the receiver can no longer recover the data. It is measured in decibels at the Nyquist frequency, and it adds up quickly. 40 dB of loss leaves the receiver with one hundredth of the signal amplitude that was sent.
At 200G per lane, IEEE 802.3dj set the reference points: up to 40 dB of loss chip to chip across a backplane, measured at 53.125 GHz, the Nyquist frequency of a 200G lane, and at least 1 m of twinax cable [6]. At 448G, the OIF wants at least that much budget, more than 40 dB over more than a metre, but at a Nyquist frequency of 75 to 112 GHz, depending on format [1].
That is the hard part, because loss rises with frequency. Skin effect pushes current to the surface of the conductor, so its loss grows roughly with the square root of frequency. Dielectric loss in the insulating material grows in direct proportion [16]. Doubling the frequency adds about 40% to the first and doubles the second. Every via, connector and transition also reflects part of the signal, and at these frequencies even small discontinuities cost margin [1].
The OIF itself is cautious. Nathan Tracy, its president, says channels at 400 gigabit "suggest that at least a meter of reach may be possible" [4]. Beyond a point, the question stops being how much equalization to add and becomes how much electrical channel the signal should cross at all [1]. That is where copper starts to move.
4. Copper does not disappear. It moves closer to the silicon
For years, a copper link meant a front-panel cable, reached from the chip through several inches of board trace. At 448G that layout stops working. PCB trace loses far more signal per inch than twinax cable, so every inch of it eats into the budget described above. The industry's answer is to take the trace out, one step at a time: hosts that use cable instead of board trace to reach the front panel, cabled backplanes, copper connected right beside the package, and finally cables that plug into the package itself [1] (Figure 2).
A 448 Gbps channel shown at DesignCon 2026 makes this concrete: 13 mm of PCB, an on-package connector, then 400 mm of low-skew cable, measured to 125 GHz [7]. Almost the entire path is cable; the board trace that remains is about half an inch.
5. Three kinds of copper, pulled apart
Copper has not been one thing for a while. A passive cable needs no powered signal conditioning; its reach depends on channel loss and host capability. A linear cable adds an equalizer or redriver but leaves signal recovery to the host: published 1.6T linear assemblies claim up to 90% lower power than DSP-based cables and under 100 ps latency [9]. Redriver silicon at 448G per channel has also been shown [10]. A retimed cable puts a DSP at each end and spends power on reach.
Current-generation products show why that distinction matters. Retimed 1.6T assemblies reach 3m at 18 to 20 W per end, while a 1.6T optical module draws 22 W typical over 500 m [11]. In this comparison, retimed copper and optics already sit in a similar power range.
At 448G, the OIF anticipates more demanding receiver processing, including maximum-likelihood detection [1]. Passive cables avoid additional processing inside the cable. Linear cables add conditioning, provided the host can still recover the signal. Retimed cables add recovery stages to support more demanding channels. The question is how much power each complete link needs, not simply whether it uses copper or optics.
And one that follows from all five: qualification
You cannot qualify for a 448G link with 224G habits. Nyquist alone lands between 75 and 112 GHz depending on modulation, and the OIF wants fixtures working well beyond the 67 GHz used at 224G [1]. Published PAM6 and PAM8 work already leans on 110 GHz scopes [13]. And one average pre-FEC BER says little once a concatenated code and burst errors are in play. That is the companion post.
The constant: power
Underneath all five sits one constraint. Between 2010 and 2022, interconnect bandwidth rose 80-fold while interconnect power rose 22-fold. At 448G the OIF expects DSP SerDes with maximum-likelihood detection, and says cutting channel loss, rather than adding repeaters, is what keeps power per bit falling [1].
So, can copper keep up?
Yes, but the channel architecture will need to evolve. For passive copper the target is still about a metre: in July 2026 IEEE adopted a 1 m twinaxial copper objective for 400G per lane [15], the same objective it set at 200G. Whether more than 40 dB at the new Nyquist can be delivered over more than a metre is still open.
Optics is moving inward from the other side. Co-packaged switches claim 3.5 times the power efficiency of pluggables, on vendor figures [12], though those are scale-out machines. Inside the rack, at today's optical power per bit, going optical would raise total power significantly [1].
The result is a continuum rather than a choice between two things, and the boundary moves inward with each generation without disappearing. Where should it sit, given bandwidth, latency, power, reach and cost?
Infraeo works across that whole continuum: passive, linear and retimed copper at 224G per lane, alongside optics. Every design is qualified on current-generation test systems and for interoperability on production switches. That gives us a practical view of the moving boundary: our job is to measure where it is, not argue where it should be. We are a US-incorporated company based in Round Rock, Texas, offering country-of-origin flexibility so customers can meet their sourcing requirements as well as their technical ones.
References
1. OIF, Next Generation CEI-448G Framework, OIF-FD-CEI-448G-01.0, 4 November 2025. https://www.oiforum.com/wp-content/uploads/OIF-FD-CEI-448G-01.0.pdf
2. NVIDIA, GB200 NVL72. https://www.nvidia.com/en-us/data-center/gb200-nvl72/
3. UALink Consortium, "UALink Consortium Releases the Ultra Accelerator Link 200G 1.0 Specification", 8 April 2025. https://ualinkconsortium.org/wp-content/uploads/2025/04/UALink-1.0-Specification-PR_FINAL.pdf
4. Gazettabyte, "448G: doing what has been done before may no longer be enough", 20 December 2025. https://gazettabyte.com/448g-doing-what-has-been-done-before-may-no-longer-be-enough/
5. C. Liu, "IEEE802.3dj Work on 200 Gbps per Lane and How Different FEC Options Affect SI", Signal Integrity Journal, 16 January 2024. https://www.signalintegrityjournal.com/articles/3405-200-gbps-ethernet-forward-error-correction-fec-analysis
6. IEEE P802.3dj Task Force, Adopted Objectives, 14 March 2024. https://www.ieee802.org/3/dj/projdoc/objectives_P802d3dj_240314.pdf
7. Samtec, "448 Gbps Co-Packaged Copper Channel", DesignCon 2026. https://www.samtec.com/support/videos/448-gbps-co-packaged-copper-channel-samtec-designcon-2026-1171891091/
8. Design World, "Samtec demonstrates 224 Gbps co-package connectors and 448 Gbps prototype at DesignCon 2026", 8 April 2026. https://www.designworldonline.com/samtec-demonstrates-224-gbps-co-package-connectors-and-448-gbps-prototype-at-designcon-2026/
9. Semtech, "Amphenol Communications Solutions and Semtech Introduce 1.6T Active Copper Cable at OFC 2025", 1 April 2025. https://www.semtech.com/company/press/amphenol-semtech-introduce-1.6t-active-copper-cable-ofc-2025
10. Semtech, "OFC 2026: Semtech Advances the Future of AI Data Center Optical and Active Copper Interconnects", March 2026. https://blog.semtech.com/ofc-2026-semtech-advances-the-future-of-ai-data-center-optical-and-active-copper-interconnects
11. Lumentum, 1.6T 2×DR4 OSFP Transceiver Module. https://www.lumentum.com/en/products/16t-2dr4-osfp-transceiver-module
12. NVIDIA, "NVIDIA Announces Spectrum-X Photonics, Co-Packaged Optics Networking Switches to Scale AI Factories to Millions of GPUs", 18 March 2025. https://nvidianews.nvidia.com/news/nvidia-spectrum-x-co-packaged-optics-networking-switches-ai-factories
13. Keysight, Research on 448 Gbps with PAM6 and PAM8, application note. https://www.keysight.com/us/en/assets/3125-1097/application-notes/Research-on-448-Gbps-with-PAM6-and-PAM8.pdf
14. K. Lusted (Synopsys), "Defining the Path to 400 Gbps-per-Lane Ethernet Signaling", Ethernet Alliance, 16 June 2026. https://ethernetalliance.org/blog/2026/06/16/defining-the-path-to-400-gbps-per-lane-ethernet-signaling/
15. IEEE 802.3 400 Gb/s/Lane Signaling Study Group, Objectives, approved by IEEE 802.3 Working Group 16 July 2026 (project P802.3dv). https://www.ieee802.org/3/400GPL/public/project_docs/400GPL_Objectives_260610.pdf
16. H. Johnson and M. Graham, High-Speed Signal Propagation: Advanced Black Magic, Prentice Hall, 2003, section 3.8, "Dielectric Loss Region". Excerpt: https://www.informit.com/articles/article.aspx?p=101149&seqNum=8
About the Author
Rohith Malkuchi is a Firmware Engineer at Infraeo Inc., where he works on high-speed interconnects for AI and data center infrastructure. His work spans firmware development, Retimer integration, CMIS compliance, and interoperability testing of 800G and 1.6T Active Electrical Cables (AECs), including validation across partner switch platforms. His technical interests include high-speed SerDes, signal integrity, emerging 224G and 448G interconnect architectures, and CPU–GPU co-design.
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